-- Registro Acumulador

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity acum is
port(RST,CLK: in std_logic;
     INPUT: in std_logic_vector (7 downto 0);
     OUTPUT: out std_logic_vector (7 downto 0));
end acum;

architecture ac_arq of acum is
begin
ac_p: process(CLK,RST)
variable cero: std_logic_vector(7 downto 0);
begin
if(RST = '1') then
   cero := "00000000";
   OUTPUT <= cero;
elsif(CLK'EVENT AND CLK = '1') then
   OUTPUT <= INPUT;
end if;

end process ac_p;
end ac_arq;
